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Titre du document / Document title

Area-delay Trade-offs of Texture Decompressors for a Graphics Processing Unit

Auteur(s) / Author(s)

NOVOA SUNER Emilio (1) ; ITUERO Pablo (1) ; LOPEZ-VALLEJO Marisa (1) ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

(1) ETSI Telecomunicación Universidad Politécnica de Madrid, ESPAGNE

Résumé / Abstract

Graphics Processing Units have become a booster for the microelectronics industry. However, due to intellectual property issues, there is a serious lack of information on implementation details of the hardware architecture that is behind GPUs. For instance, the way texture is handled and decompressed in a GPU to reduce bandwidth usage has never been dealt with in depth from a hardware point of view. This work addresses a comparative study on the hardware implementation of different texture decompression algorithms for both conventional (PCs and video game consoles) and mobile platforms. Circuit synthesis is performed targeting both a reconfigurable hardware platform and a 90nm standard cell library. Area-delay trade-offs have been extensively analyzed, which allows us to compare the complexity of decompressors and thus determine suitability of algorithms for systems with limited hardware resources.

Revue / Journal Title

Proceedings of SPIE, the International Society for Optical Engineering    ISSN  0277-786X   CODEN PSISDG 

Source / Source

Congrès
VLSI circuits and systems V :   ( 18-20 April 2011, Prague, Czech Republic )
VLSI circuits and systems. Conference No05, Prague , TCHEQUE, REPUBLIQUE (18/04/2011)
2011  , vol. 8067[Note(s) : 1 vol., ] (7 ref.) ISBN 978-0-8194-8656-1 ;  Illustration : Illustration ;

Langue / Language

Anglais

Editeur / Publisher

Society of Photo-Optical Instrumentation Engineers, Bellingham, WA, ETATS-UNIS  (1981) (Revue)
SPIE, Bellingham WA, ETATS-UNIS  (2011) (Monographie)

Mots-clés anglais / English Keywords

Standard cell library

;

Integrated circuit design

;

Logic design

;

Reconfigurable architectures

;

Circuit synthesis

;

Algorithm

;

Comparative study

;

Implementation

;

Intellectual property

;

Microelectronics

;

Graphic processing unit

;

Delay time

;

Mots-clés français / French Keywords

Bibliothèque cellule standard

;

Conception circuit intégré

;

Conception logique

;

Architecture reconfigurable

;

Synthèse circuit

;

Algorithme

;

Etude comparative

;

Implémentation

;

Propriété intellectuelle

;

Microélectronique

;

Carte graphique

;

Temps retard

;

Mots-clés espagnols / Spanish Keywords

Circuito célula estándar

;

Concepción lógica

;

Síntesis circuito

;

Algoritmo

;

Estudio comparativo

;

Implementación

;

Propiedad intelectual

;

Microelectrónica

;

Unidad de proceso gráfico

;

Tiempo retardo

;

Localisation / Location

INIST-CNRS, Cote INIST : 21760, 35400017475196.0210

Nº notice refdoc (ud4) : 24588414



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