Titre du document / Document title

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

Auteur(s) / Author(s)

MARTENS Koen ^{(1 2)} ; CHI ON CHUI ⁽³⁾ ; BRAMMERTZ Guy ⁽⁴⁾ ; DE JAEGER Brice ⁽⁴⁾ ; KUZUM Duygu ⁽¹⁾ ; MEURIS Marc ⁽⁴⁾ ; HEYNS Marc M. ⁽⁴⁾ ; KRISHNAMOHAN Tejas ⁽⁵⁾ ; SARASWAT Krishna ; MAES Herman E. ^{(2 4)} ; GROESENEKEN Guido ^{(2 4)} ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

⁽¹⁾ Stanford University, Palo Alto, CA 94305, ETATS-UNIS
⁽²⁾ ESAT Laboratory, Katholieke Universiteit(K.U.) Leuven, 3001 Leuven, BELGIQUE
⁽³⁾ Department of Electrical Engineering, University of California, Los Angeles, CA 90095, ETATS-UNIS
⁽⁴⁾ Interuniversity Microelectronics Center (IMEC), 3001 Leuven, BELGIQUE
⁽⁵⁾ Intel Corporation, Santa Clara, CA 95054, ETATS-UNIS

Résumé / Abstract

"Conventional" techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance- and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Revue / Journal Title

I.E.E.E. transactions on electron devices   ISSN 0018-9383   CODEN IETDAI 

Source / Source

2008, vol. 55, n^o2, pp. 547-556 [10 page(s) (article)] (28 ref.)

Langue / Language

Anglais

Editeur / Publisher

Institute of Electrical and Electronics Engineers, New York, NY, ETATS-UNIS  (1963) (Revue)

Mots-clés anglais / English Keywords

III-V compound ; MOSFET ; Electrical characteristic ; Voltage capacity curve ; MOS structure ; Charge carrier trapping ; Density of states ; Interface state ;

Mots-clés français / French Keywords

Composé III-V ; Transistor MOSFET ; Caractéristique électrique ; Caractéristique capacité tension ; Structure MOS ; Piégeage porteur charge ; Densité état ; Etat interface ;

Mots-clés espagnols / Spanish Keywords

Compuesto III-V ; Característica eléctrica ; Característica capacidad tensión ; Estructura MOS ; Captura portador carga ; Densidad estado ; Estado interfase ;

Mots-clés d'auteur / Author Keywords

III-V ; alternative substrates ; conductance method ; electrical characterization ; Ge MOSFET ; interface trap density extraction ; Nicollian-Goetzberger ;

Localisation / Location

INIST-CNRS, Cote INIST : 222 F3, 35400018343724.0120