Titre du document / Document title

Radix-16 signed-digit division

Auteur(s) / Author(s)

CARTER T. M. ; ROBERTSON J. E. ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

Univ. Utah, dep. computer sci., Salt Lake City UT 84112, ETATS-UNIS

Résumé / Abstract

For use in the context of a linearly scalable arithmetic architecture supporting high/variable precision arithmetic operations (integer or fractional), a two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm use two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit. The algorithm requires a two-digit estimate of the (initial) partial remainder and a three-digit estimate of the divisor to correctly select each successive quotient digit. The normalization of redundant signed-digit numbers requires accommodation of some fuzzines at one end of the range of numeric values that are considered normalized. A set of general equations for determining the ranges of normalized signed-digit numbers is derived. Another set of general equations for determining the precisions of estimates of the divisor and dividend required in a limited precision SRT model signed-digit division are derived. These two sets of equations permit design tradeoff analyses to be made with respect to the complexity of the model division. The specific case of a two-stage radix-16 signed-digit division is presented. The staged division algorithm used can be extended to other radices as long as the signed-digit number representation used has certain properties

Revue / Journal Title

IEEE transactions on computers   ISSN 0018-9340   CODEN ITCOB4 

Source / Source

1990, vol. 39, n^o12, pp. 1424-1433 [10 page(s) (article)] (29 ref.)

Langue / Language

Anglais

Editeur / Publisher

Institute of Electrical and Electronics Engineers, New York, NY, ETATS-UNIS  (1968) (Revue)

Mots-clés anglais / English Keywords

Variable ; Accuracy ; Computer architecture ; Arithmetic unit ; Algorithm ; Representation ; Number ; Division ; Computers arithmetic ; Computer theory ; Variable ; Accuracy ; Computer architecture ; Arithmetic unit ; Algorithm ; Representation ; Number ; Division ; Computers arithmetic ; Computer theory ; Variable ; Accuracy ; Computer architecture ; Arithmetic unit ; Algorithm ; Representation ; Number ; Division ; Computers arithmetic ; Computer theory ;

Mots-clés français / French Keywords

Variable ; Précision ; Architecture ordinateur ; Unité arithmétique ; Algorithme ; Représentation ; Nombre ; Division ; Arithmétique ordinateur ; Informatique théorique ; Variable ; Précision ; Architecture ordinateur ; Unité arithmétique ; Algorithme ; Représentation ; Nombre ; Division ; Arithmétique ordinateur ; Informatique théorique ; Variable ; Précision ; Architecture ordinateur ; Unité arithmétique ; Algorithme ; Représentation ; Nombre ; Division ; Arithmétique ordinateur ; Informatique théorique ;

Mots-clés espagnols / Spanish Keywords

Variable ; Precisión ; Arquitectura ordenador ; Unidad aritmética ; Algoritmo ; Representación ; Número ; División ; Aritmética ordenador ; Informática teórica ; Variable ; Precisión ; Arquitectura ordenador ; Unidad aritmética ; Algoritmo ; Representación ; Número ; División ; Aritmética ordenador ; Informática teórica ; Variable ; Precisión ; Arquitectura ordenador ; Unidad aritmética ; Algoritmo ; Representación ; Número ; División ; Aritmética ordenador ; Informática teórica ;

Localisation / Location

INIST-CNRS, Cote INIST : 222 F4,