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Titre du document / Document title

Investigations on the reliability of lead-free CSP subjected to harsh environments

Auteur(s) / Author(s)

DUDEK Rainer (1) ; DÖRING Ralf (1) ; MICHEL Berad (1) ; PETZOLD Gunnar (2) ; ALBRECHT Juergen (2) ; WIEAND Christian (3) ; KUHN Stefan (3) ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

(1) Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (IZM) Micro Materials Center Chemnitz Otto-Schmerbach-Str. 19, 09117 Chemnitz, ALLEMAGNE
(2) Siemens AG, Berlin, ALLEMAGNE
(3) Siemens VDO Automotive AG, Regensburg, ALLEMAGNE

Résumé / Abstract

A study of the performance of Flip-Chip Chip-Scale Packages (FC-CSPs) with lead-free solder interconnects was undertaken. The parametric studies on the CSPs were performed considering a wide variation of geometric and material parameters. Two geometrical versions on organic interposer with different die sizes were investigated theoretically and experimentally by thermal cycling tests -40 °C to 150 °C. In the FE-analyses, several additional parameters were examined including BT-interposer thickness, standoff, perimeter vs. full array, and solder-mask defined vs. non-solder-mask defined (NSMD) balls. Underfilling of the CSPs was an additional option. In the finite element analyses (FEA) both SnAg and SnAgCu solders were considered. For the latter a newly developed combined primary-secondary creep law was applied in the calculations. Both the inelastic strain (creep strain) and dissipated strain energy density represent suitable indicators to evaluate cyclic damage. It is demonstrated that for a thermal test cycle both measures result in similar critical cycle numbers. The calculations show that the creep strain always concentrates at the interfaces of the balls to the package. Maximum straining typically occurs at the inner ball row. Major effects on ball fatigue life are shown to be standoff height, ball geometry on both sides non solder mask defined (NSMD), and a stiff underfill. It is also shown that the CSP reliability using a soft underfill with high CTE or a similar avarage soft underfill layer, composed of the soldermask layers and the underfill itself, can be worse than for a non-underfilled CSP. Testing results are compared to theoretical predictions. In many cases they agree reasonably well. Finally, differences between simulation and testing results are discussed.

Source / Source

Congrès
ITherm 2004 :   ( Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems )  ( Mirage Hotel & Casino, Las Vegas, NV, June 1-June 4, 2004 )
InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems No9, Las Vegas NV , ETATS-UNIS (2004)
2004  [Note(s) : 2 vol.(XXIX-748 ; 758 p.), ] (7 ref.), [Notes: "IEEE Catalog Number: 04CH37543"--P. ii] ISBN 0-7803-8357-5 ;  Illustration : Illustration ;

Langue / Language

Anglais

Editeur / Publisher

IEEE, Piscataway NJ, ETATS-UNIS  (2004) (Monographie)

Mots-clés anglais / English Keywords

Durability

;

Integrated circuit

;

Integrated circuit bonding

;

Solder metal

;

Fatigue life

;

Electronic packaging

;

Damaging

;

Energy dissipation

;

Inelasticity

;

Creep

;

Finite element method

;

Numerical method

;

Soldered joint

;

Thermal cycle

;

Thermal test

;

Die

;

Parametric analysis

;

Interconnection

;

Lead free soldering

;

Flip-chip

;

Performance evaluation

;

Hostile environment

;

Chip scale packaging

;

Reliability

;

Mots-clés français / French Keywords

Durabilité

;

Circuit intégré

;

Assemblage circuit intégré

;

Métal fondu brasage tendre

;

Durée vie fatigue

;

Packaging électronique

;

Endommagement

;

Dissipation énergie

;

Inélasticité

;

Fluage

;

Méthode élément fini

;

Méthode numérique

;

Assemblage brasage tendre

;

Cycle thermique

;

Essai thermique

;

Matrice formage

;

Analyse paramétrique

;

Interconnexion

;

Brasage sans plomb

;

Puce à bosses

;

Evaluation performance

;

Environnement hostile

;

Technologie CSP

;

Fiabilité

;

Mots-clés espagnols / Spanish Keywords

Durabilidad

;

Circuito integrado

;

Metal fundido soldeo blando

;

Longevidad fatiga

;

Packaging electrónico

;

Deterioración

;

Disipación energía

;

Inelasticidad

;

Fluencia

;

Método elemento finito

;

Método numérico

;

Junta soldada

;

Ciclo térmico

;

Prueba térmica

;

Matriz formadora

;

Interconexión

;

Soldeo sin plomo

;

Evaluación prestación

;

Medio ambiente hóstil

;

Fiabilidad

;

Localisation / Location

INIST-CNRS, Cote INIST : Y 38768(1), 35400013873386.1190

Nº notice refdoc (ud4) : 17808443



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