Titre du document / Document title

Ring oscillators for CMOS process tuning and variability control

Auteur(s) / Author(s)

BHUSHAN Manjul ⁽¹⁾ ; GATTIKER Anne ⁽²⁾ ; KETCHEN Mark B. ⁽³⁾ ; DAS Koushik K. ⁽⁴⁾ ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

⁽¹⁾ IBM Systems and Technology Group, Poughkeepsie, NY 12601, ETATS-UNIS
⁽²⁾ IBM Research Division, Austin Research Lab, Austin, TX 78758, ETATS-UNIS
⁽³⁾ IBM Research Division, Hopewell Junction, NY 12533, ETATS-UNIS
⁽⁴⁾ IBM Research Division, Yorktown Heights, NY 10598, ETATS-UNIS

Résumé / Abstract

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator (PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

Revue / Journal Title

IEEE transactions on semiconductor manufacturing    ISSN  0894-6507 

Source / Source

Congrès
International Conference on Microelectronic Test Structures (ICMTS) N^o18, Leuven , BELGIQUE (2005)
2006, vol. 19, n^o1, pp. 10-18 [9 page(s) (article)] (5 ref.)

Langue / Language

Anglais

Editeur / Publisher

Institute of Electrical and Electronics Engineers, New York, NY, ETATS-UNIS  (1988) (Revue)

Mots-clés anglais / English Keywords

Modeling

;

Integrated circuit

;

Integrated circuit manufacture

;

Sensitivity analysis

;

Network analysis

;

Delay circuit

;

Data analysis

;

Silicon on insulator technology

;

Depletion layer

;

Delay time

;

Performance evaluation

;

Switching conditions

;

CMOS integrated circuits

;

Digital circuit

;

MOSFET

;

Ring structure

;

Testing equipment

;

Complementary MOS technology

;

Ring oscillator

;

Mots-clés français / French Keywords

Modélisation

;

Circuit intégré

;

Fabrication circuit intégré

;

Analyse sensibilité

;

Analyse circuit

;

Circuit retard

;

Analyse donnée

;

Technologie silicium sur isolant

;

Couche appauvrissement

;

Temps retard

;

Evaluation performance

;

Régime commutation

;

Circuit intégré CMOS

;

Circuit numérique

;

Transistor MOSFET

;

Structure annulaire

;

Appareillage essai

;

Technologie MOS complémentaire

;

Oscillateur anneau

;

Mots-clés espagnols / Spanish Keywords

Modelización

;

Circuito integrado

;

Análisis sensibilidad

;

Análisis circuito

;

Circuito retardo

;

Análisis datos

;

Tecnología silicio sobre aislante

;

Capa empobrecimiento

;

Tiempo retardo

;

Evaluación prestación

;

Régimen conmutación

;

Circuito numérico

;

Estructura anular

;

Aparato ensayo

;

Tecnología MOS complementario

;

Oscilador anillo

;

Mots-clés d'auteur / Author Keywords

Circuit sensitivity analysis

;

CMOS integrated circuits

;

CMOSFET oscillators

;

integrated circuit manufacture

;

integrated circuit modeling

;

process monitoring

;

Localisation / Location

INIST-CNRS, Cote INIST : 21454, 35400011515153.0020