Titre du document / Document title

20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits

Auteur(s) / Author(s)

ITO Maki ⁽¹⁾ ; KAWASAKI Kenji ⁽¹⁾ ; YOSHIKAWA Nobuyuki ⁽¹⁾ ; FUJIMAKI Akira ⁽²⁾ ; TERAI Hirotaka ⁽³⁾ ; YOROZU Shinich ⁽⁴⁾ ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

⁽¹⁾ Department of Electrical and Computer Engineering, Yokohama National University, Yokohama, 240- 8501, JAPON
⁽²⁾ Department of Quantum Engineering, Nagoya University, Nagoya, 464-8603, JAPON
⁽³⁾ National Institute of Information and Communication Technology, Kobe, 651-2492, JAPON
⁽⁴⁾ International Superconductivity Technology Center Superconductivity Research Laboratory, Tsukuba, 305-8501, JAPON

Résumé / Abstract

Synchronous design is generally used in SFQ digital systems at present. In large-scale SFQ digital systems, however, the introduction of asynchronous design is required due to the large clock skew in the clock distribution network and complexity in the timing design at high clock rate. We have proposed a hierarchical design approach using asynchronous SFQ circuits with handshaking protocol for asynchronous data transfer. In our asynchronous approach, each circuit module is designed based on a data driven self-timed (DDST) architecture. A handshaking protocol is also used to ensure the logical ordering in data communication between the modules, where we have adopted bit-serial architecture to reduce the communication costs in handshaking. One issues in the bit-serial handshaking (BSHS) system is the synchronization of the input data when the module has multiple input ports. In this study, we have designed an SFQ BSHS system with multiple input ports, where Muller C-elements is used to synchronize the multiple input data. We have designed and implemented a BSHS half adder using NEC 2.5 kA/cm² Nb standard process to demonstrate asynchronous addition of two input data at high speed. We have successfully confirmed its correct operation at about 20 GHz.

Revue / Journal Title

IEEE transactions on applied superconductivity   ISSN 1051-8223 

Source / Source

Congrès
2004 Applied Superconductivity Conference, Jacksonville, FL , ETATS-UNIS (03/10/2004)
2005, vol. 15 (1), n^o 2 (1000 p.)  [Document : 4 p.] (9 ref.), pp. 255-258 [4 page(s) (article)]

Langue / Language

Anglais

Editeur / Publisher

Institute of Electrical and Electronics Engineers, New York, NY, ETATS-UNIS  (1991) (Revue)

Mots-clés anglais / English Keywords

Arithmetic circuit ; Integrated circuit ; Economic aspect ; Electrical network ; High speed ; Adder ; Implementation ; Multiple system ; Synchronization ; Cost minimization ; Data communication ; Ordering ; Circuit design ; Data transmission ; Clock ; Distribution network ; Delay time ; Large scale ; Digital system ; Logic circuit ; Superconducting integrated circuits ; Asynchronous circuit ;

Mots-clés français / French Keywords

Circuit arithmétique ; Circuit intégré ; Aspect économique ; Réseau électrique ; Grande vitesse ; Additionneur ; Implémentation ; Système multiple ; Synchronisation ; Minimisation coût ; Communication donnée ; Relation ordre ; Conception circuit ; Transmission donnée ; Horloge ; Réseau distribution ; Temps retard ; Echelle grande ; Système numérique ; Circuit logique ; Circuit intégré supraconducteur ; Circuit asynchrone ;

Mots-clés espagnols / Spanish Keywords

Circuito aritmético ; Circuito integrado ; Aspecto económico ; Red eléctrica ; Gran velocidad ; Adicionador ; Implementación ; Sistema múltiple ; Sincronización ; Minimización costo ; Relación orden ; Diseño circuito ; Transmisión datos ; Reloj ; Red distribución ; Tiempo retardo ; Escala grande ; Sistema numérico ; Circuito lógico ; Circuito asincrono ;

Mots-clés d'auteur / Author Keywords

Adder ; asynchronous system ; bit-serial architecture ; data-driven self-timing ; handshaking ; SFQ circuit ;

Localisation / Location

INIST-CNRS, Cote INIST : 22424, 35400013813911.0450