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Titre du document / Document title

Chip-in-polymer: Volumetric packaging solution using PCB technology

Auteur(s) / Author(s)

JUNG Erik (1) ; WOJAKOWSKI Dirk (1) ; NEUMANN Alexander (1) ; LANDESBERGER Christof (1) ; OSTMANN Andreas (1) ; ASCHENBRENNER Rolf (1) ; REICHL Herbert (1) ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

(1) FhG-IZM, TU Berlin, Gustav-Meyer-Allee 25, 13355 Berlin, ALLEMAGNE

Résumé / Abstract

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). Here, use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems make use of single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but as well active circuitry (IC's) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB' s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. As a ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first attempts to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable box-of-bricks type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA utilizing low cost technologies derived from the PCB manufacturing industry.

Revue / Journal Title

IEEE/CPMT International Electronics Manufacturing Technology Symposium    ISSN  1089-8190 

Source / Source

Congrès
IEMT 2002 : international electronics manufacturing technology symposium :   ( San Jose CA, 17-18 July 2002 )
IEEE / CPMT / SEMI annual international electronics manufacturing technology symposium No27, San Jose CA , ETATS-UNIS (17/07/2002)
2002  , pp. 46-49[Note(s) : IV, 428 p., ] [Document : 4 p.] (22 ref.) ISBN 0-7803-7301-4 ;  Illustration : Illustration ;

Langue / Language

Anglais

Editeur / Publisher

IEEE, Piscataway NJ, ETATS-UNIS  (2002) (Monographie)

Mots-clés anglais / English Keywords

Stratified material

;

Dielectric materials

;

Ultrathin films

;

Polymer

;

Soldered joint

;

Integrated circuit bonding

;

Integrated circuit

;

Printed circuit

;

Microelectronic fabrication

;

BGA technology

;

Interconnection

;

Electric contact

;

Embedded transducer

;

Micromachine

;

Die

;

Thermal behavior

;

Passive component

;

System on a chip

;

Subsystem

;

Miniaturization

;

Autonomous system

;

Printed circuit board

;

Electronic packaging

;

Mots-clés français / French Keywords

Matériau stratifié

;

Diélectrique

;

Couche ultramince

;

Polymère

;

Assemblage brasage tendre

;

Assemblage circuit intégré

;

Circuit intégré

;

Circuit imprimé

;

Fabrication microélectronique

;

Technologie BGA

;

Interconnexion

;

Contact électrique

;

Transducteur enfoui

;

Micromachine

;

Matrice formage

;

Comportement thermique

;

Composant passif

;

Système sur puce

;

Sous système

;

Miniaturisation

;

Système autonome

;

Carte électronique

;

Packaging électronique

;

Mots-clés espagnols / Spanish Keywords

Material estratificado

;

Dieléctrico

;

Polímero

;

Junta soldada

;

Circuito integrado

;

Circuito imprimido

;

Fabricación microeléctrica

;

Tecnología BGA

;

Interconexión

;

Contacto eléctrico

;

Transductor embebido

;

Micromáquina

;

Matriz formadora

;

Comportamiento térmico

;

Componente pasivo

;

Sistema sobre pastilla

;

Subsistema

;

Miniaturización

;

Sistema autónomo

;

Tarjeta electronica

;

Packaging electrónico

;

Localisation / Location

INIST-CNRS, Cote INIST : Y 37918, 35400011775765.0070

Nº notice refdoc (ud4) : 15716166



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