Titre du document / Document title

III-V quantum devices and circuits based on nanoscale Schottky gate control of hexagonal quantum wire networks

Auteur(s) / Author(s)

KASAI Seiya ⁽¹⁾ ; HASEGAWA Hideki ⁽¹⁾ ;

Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)

⁽¹⁾ Research Center for Integrated Quantum Electronics and Graduate School of Electronics and Information Engineering, Hokkaido University, N-13 W-8, Kita-ku, Sapporo 060-8628, JAPON

Résumé / Abstract

The concept, the present status, key issues and future prospects of a novel hexagonal binary decision diagram (BDD) quantum circuit approach for III-V quantum large-scale integrated circuits (QLSIs) are presented and discussed. In this approach, the BDD logic circuits are implemented on III-V semiconductor-based hexagonal nanowire networks controlled by nanoscale Schottky gates. The hexagonal BDD QLSIs can operate at delay-power products near the quantum limit in the quantum regime as well as in the many-electron classical regime. To demonstrate the feasibility of the present approach, GaAs Schottky wrap gate (WPG)-based single-electron BDD node devices and their integrated circuits were fabricated and their proper operations were confirmed. Selectively grown InGaAs sub-10 nm quantum wires and their hexagonal networks have been investigated to form high-density hexagonal BDD QLSIs operating in the quantum regime at room temperature.

Revue / Journal Title

Applied surface science   ISSN 0169-4332 

Source / Source

Congrès
ICFSI-8 International Conference on the Formation of Semiconductor Interfaces N^o8, Sapporo , JAPON (10/06/2001)
2002, vol. 190, n^o 1-4 (562 p.)  (21 ref.), pp. 176-183

Langue / Language

Anglais

Editeur / Publisher

Elsevier, Amsterdam, PAYS-BAS  (1985) (Revue)

Mots-clés anglais / English Keywords

Schottky barrier ; Binary decision diagram ; Nanoelectronics ; Quantum well ; Nanostructured materials ; Logic circuit ; Integrated circuit ; Quantum wire ; III-V semiconductors ;

Mots-clés français / French Keywords

Barrière Schottky ; Diagramme binaire décision ; Nanoélectronique ; Puits quantique ; Nanomatériau ; Circuit logique ; Circuit intégré ; Fil quantique ; Semiconducteur III-V ;

Mots-clés espagnols / Spanish Keywords

Barrera Schottky ; Diagrama binaria decisión ; Nanoelectrónica ; Pozo cuántico ; Circuito lógico ; Circuito integrado ; Hilo cuántico ;

Localisation / Location

INIST-CNRS, Cote INIST : 16002, 35400010161710.0310